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| 8-BIT SHIFT REGISTER FEATURES s s s s s s s s s s Max. shift frequency of 600MHz Max. Clock to Q delay of 1200ps IEE min. of -150mA Industry standard 100K ECL levels Extended supply voltage option: VEE = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity Internal 75K input pull-down resistors 70% faster than Fairchild 300K at lower power Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages SY100S341 DESCRIPTION The SY100S341 offer eight D-type, edge-triggered flipflops with both individual inputs for parallel operation as well as serial inputs for bidirectional shifting, and are designed for use in high-performance ECL systems. Data is clocked into the flip-flops on the rising edge of the clock. The mode of operation is selected by two Select inputs (S0, S1) which determine if the device performs a shift, hold or parallel entry function, as described in the Truth Table. The inputs on these devices have 75K pull-down resistors. PIN CONFIGURATIONS P6 P7 VEES Q7 Q6 4 3 2 1 28 27 26 11 10 9 8 7 6 5 P4 CP VEE VEES S0 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Top View PLCC J28-1 Q5 Q4 VCCA VCC VCC Q3 Q2 PIN NAMES Label CP S0 -- S1 D0 -- D7 P0 -- P7 Q0 -- Q7 VEES VCCA Function Clock Pulse Input Select Inputs S1 P3 D7 P5 S1 S0 VEE CP P3 P2 P1 P0 VEES Serial Inputs Parallel Inputs Data Outputs VEE Substrate VCCO for ECL Outputs D0 Q0 Q1 P2 P1 P0 D0 Q0 Q1 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 P4 P5 P6 P7 D7 Q7 Q8 13 7 8 9 10 11 12 Q3 VCC VCCA Q2 Q4 Q5 Rev.: G Amendment: /0 1 Issue Date: July, 1999 Micrel SY100S341 BLOCK DIAGRAM D7 DQ C Q7 P7 Q D C Q6 P6 Q1 Q D C P1 PARALLEL LOAD SHIFT LEFT SHIFT RIGHT HOLD Q D C Q0 P0 DECODE S0 S1 D0 CP 2 Micrel SY100S341 TRUTH TABLE Inputs Function Load Register Shift Left Shift Left Shift Right Shift Right Hold Hold Hold NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care u = LOW-to-HIGH Transition Outputs S0 L H H L L H X X CP u u u u u X H L Q7 P7 Q6 Q6 L H Q6 P6 Q5 Q5 Q7 Q7 Q5 P5 Q4 Q4 Q6 Q6 Q4 P4 Q3 Q3 Q5 Q5 Q3 P3 Q2 Q2 Q4 Q4 Q2 P2 Q1 Q1 Q3 Q3 Q1 P1 Q0 Q0 Q2 Q2 Q0 P0 L H Q1 Q1 D7 X X X L H X X X D0 X L H X X X X X S1 L L L H H H X X No Change DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current, All Inputs Power Supply Current Min. -- -150 Typ. -- -102 Max. 200 -71 Unit A mA Condition VIN = VIH (Max.) Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol fshift tPLH tPHL tTLH tTHL tS Parameter Shift Frequency Propagation Delay CP to Output Transition Time 20% to 80%, 80% to 20% Set-up Time Dn, Pn Sn Hold Time Dn, Pn Sn Pulse Width HIGH, CP Min. 600 450 300 Max. -- 1200 900 TA = +25C Min. 600 450 300 Max. -- 1200 900 TA = +85C Min. 600 450 300 Max. -- 1200 900 Unit MHz ps ps ps 300 600 300 0 -- -- -- -- -- 600 300 600 300 0 -- -- -- -- -- 600 300 600 300 0 -- -- -- ps -- -- 600 ps Condition tH tpw (H) 3 Micrel SY100S341 AC ELECTRICAL CHARACTERISTICS PLCC VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol fshift tPLH tPHL tTLH tTHL tS Parameter Shift Frequency Propagation Delay CP to Output Transition Time 20% to 80%, 80% to 20% Set-up Time Dn, Pn Sn Hold Time Dn, Pn Sn Pulse Width HIGH, CP Min. 600 450 300 Max. -- 1200 900 TA = +25C Min. 600 450 300 Max. -- 1200 900 TA = +85C Min. 600 450 300 Max. -- 1200 900 Unit MHz ps ps ps 300 600 300 0 -- -- -- -- -- 600 300 600 300 0 -- -- -- -- -- 600 300 600 300 0 -- -- -- ps -- -- 600 ps Condition tH tpw (H) TIMING DIAGRAMS 0.7 0.1 ns 0.7 0.1 ns -0.95V 80% 50% 20% -1.69V 1/fshift tpw (H) -0.95V PARALLEL -1.69V tPLH tPHL CLOCK OUTPUT tTLH tTHL Propagation Delay and Transition Times 4 Micrel SY100S341 TIMING DIAGRAMS -0.95V Pn, Sn, Dn 50% -1.69V tH tS -0.95V CLOCK 50% -1.69V Set-up and Hold Times NOTES: 1. VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND. 2. tS is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code SY100S341FC SY100S341JC SY100S341JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 5 Micrel SY100S341 24 LEAD CERPACK (F24-1) Rev. 03 6 Micrel SY100S341 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 7 |
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